Hmmm... I'd have to look at the schematic. Either the ULA has to pause the CPU or the buss runs at double speed and the ULA and CPU alternate clock cycles.mmu_man wrote:Except the RDY pin which IIRC can be used to step the cpu is just grounded, doesn't come from the ULA.
Besides, the ULA can't stop doing the display, and the cpu will probably not like loosing it's clock. It can be done maybe but would need complex circuits to make sure it's safe (cf http://www.6502.org/mini-projects/clock ... ching.html ).
It may not be possible without some cutting and soldering and I don't think people would find that acceptable.
It would be a possible enhancement if someone implemented the ORIC in an FPGA though.
I'm interested to see what alternatives people come up with. It wouldn't hurt to have a few choices.