ROM RAM Extentions

This is the right place to discuss on how to implement hardware vsync, adding a VIA or AY chipset, puting multiple roms, or how to design a new flash expansion card.
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ralle
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ROM RAM Extentions

Post by ralle »

Hi there,
I would like to connect external ROM and RAM (static) to an Oric-1 16K. The lines / MAP and O1 (O2) are used for this purpose. How do I have to understand these lines?
An external ROM idea would be the Diagnostic ROM and possibly the EXBASIC 1.1. Since the structure is similar to that of the GDR home computer, from C000h BASIC and operating system, something like this should work. Also a memory expansion for the rare ORIC-1 16K.

https://www.sax.de/~zander/z9001/module ... _bas8s.pdf

For the first idea, I have an adaptation of this module in mind. Only a 10K area is displayed here, the 10K KC-BASIC, but that is the least of the problems. The module addresses 16 K, only 10k are used here. The logic gates could be replaced by diodes. The D8205 is compatible with the 74ls138. A 74ls541 can be used as a possible driver if only one EPROM does.

Gruß Ralle

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kenneth
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Re: ROM RAM Extentions

Post by kenneth »

Hallo und willkommen Doc.

I think that you can use a D toggle writable at page3 of the memory, the contain of this little register will select the external memory to enable at #C000 to #FFFF memory location. The MAP signal is not necessary to do that. :wink:

ralle
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Re: ROM RAM Extentions

Post by ralle »

First I had to think about what was meant by D-toggle, i.e. a flip-flop. But what is meant on page 3 is still a mystery to me. The presented plan can be used as an aid to find a solution. Well, the 6502 is a bit different than the Z 80. Although I usually have a clone of the Z80. The 74138 is actually an address decoder, which in this case can address 16KB from a start address.

https://www.robotrontechnik.de/bilder/U ... 9k_e2t.jpg

Here you can see a ROM-BASIC module for the Z1013. The manufacturer didn't have that, it had to be built by yourself. The start address here is C000h. The control of the ChipSelect by the address decoder via diodes is interesting here. Apart from the fact that the circuit diagram has a serious flaw, the circuit works quite well on one. With this computer kit, the / MEMDIS must be generated dynamically. At first, it doesn't play a role at ORIC. The address decoder is important. 2 NAND so 1 7400 and the 74138 are enough. In this case a / ROMDIS can be carried out statically.

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Dbug
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Re: ROM RAM Extentions

Post by Dbug »

ralle wrote:
Sun Nov 21, 2021 8:16 pm
But what is meant on page 3 is still a mystery to me.
Page 3 is the 256 bytes area from $300 to $3FF where all the I/O registers (VIA, Floppy Disk Controller, ...) are mapped.
https://wiki.defence-force.org/doku.php ... page_3_i_o

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iss
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Re: ROM RAM Extentions

Post by iss »

Hallo, @ralle! Welcome here at DF-forum.

This is the simplest example how to connect external ROM to Oric - you need only 1/2 of a 7400:
(It's part of the @mikeb's Oric Diag Board and I used it to quickly strip it to what you need. The same 'solution' is present in many other extensions.)
rom.jpg

If you want to connect exactly den ROM-BASIC Modul fuer den Z1013, here is the modified schematic:
9k_e2t-mod.jpg
It will be really interesting to see how eine VEB Robotron platine works with Oric ;).
Keep going and post feedback with the results!

ralle
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Re: ROM RAM Extentions

Post by ralle »

I could try that. The first drawing addresses the 16K EPROM from C000h, as I can see. And therefore far easier than that of the Z1013. The problem with the Z1013 is that there is a 1K image memory in the 16K block from EC00h to F000h. That's why I had to castrate the 2nd 2716 in half during the replica. He had faded into the image memory and made crap. This is very easy to do by setting address pin 10 (pin 19) to GND.

But that shouldn't really be a problem with ORIC. The advantage here is that the GDR home computers have almost the same structure.

ralle
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Re: ROM RAM Extentions

Post by ralle »

Dbug wrote:
Sun Nov 21, 2021 8:35 pm
ralle wrote:
Sun Nov 21, 2021 8:16 pm
But what is meant on page 3 is still a mystery to me.
Page 3 is the 256 bytes area from $300 to $3FF where all the I/O registers (VIA, Floppy Disk Controller, ...) are mapped.
https://wiki.defence-force.org/doku.php ... page_3_i_o
thanks...

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