Chema wrote: ↑Thu Aug 27, 2020 11:22 pm
One stupid idea..
Not a stupid idea!
Address lines A0-A15 (as on the CPU and expansion port) are not affected by the ULA (ULA only reads A15-A8, and doesn't connect to A7-A0). So activity on any of the address lines indicates running CPU. Although, if the CPU reads "bad code" from memory, it will quickly crash and stop doing that. (Hence the Diag rom staying in ROM until sure that the RAM works, and *definitely* staying in ROM twiddling thumbs when RAM failed!)
6502 crashes the moment it reads any memory location holding a byte ending in 2 (#02, #12 ...) apart from #A2 (a legit opcode). You'll hit one eventually.
ULA reads then screen memory "in secret" directly by hijacking the Row/Column addresses while the CPU is shut out. CPU has no idea this happens.
You could check for scope (or logic probe at a push) activity at every one of: ULA Pins 38,36,37,4,3,2,40,39 (which should be all active all the time with Row and Col addresses, even with a dead CPU), and also IC8 pins 7,4,12,9 and IC 20 pins 7,4,12,9 (output from the multiplexer to DRAM). A mysterious loss of "activity" here indicates the multiplexer isn't happy any more.
The CPU, when running, pulses the SYNC pin (pin 7 of CPU, not shown on Oric schematic, as it's not used). Again, that will stop quickly if the CPU crashes or never starts
A scope is very handy if available. Clock going into the CPU (p37)/out of the CPU (pin 3, 39) all at 1MHz. Data bus/Address bus -- if any one line within a bus looks very different to the others, something may be holding it down or up. Or just letting it float about.
Dumb stuff: like pin 40 of the CPU shorted to ground (never ending reset ...) would spoil your day too.