Can't answer for ISS's ROM, but when you say "got nothing", you must have a VERY early failure in the tests that are so bad I couldn't get a message up on screen. See the documentation -- error codes are put onto the address bus.
"A RAM test will be performed and a message put on screen showing if this passes. In the event of a test
failure, the ROM is designed to go into a loop with A15-A8 all logic “1”, A7-A2 will have stable logic
levels indicating a status code (also visible on LEDs if using external board). A1 and A0 will be
cycling rapidly."
What does your scope/probe show is happening on the address bus after boot?
No messing about involved, I go straight to a quick initial test of two page zero locations required for indexing, unlike the one in Oric which seems to assume it will all just work
"If the test runs and fails it exits with status code 1 (Quick RAM test fail). As described, the address
lines will be in a stable state (A15-A8 high, A7-A2 will be 000001, A1-A0 pulsing)."
Then a full RAM test is done, failure will be A7-A2 as 000010 ...
I figured, there's no point loading character sets and setting up the screen if I can't even read/write RAM
Code: Select all
; Cold Reset/Startup comes here
vect_reset:
SEI ; Turn off interrupts
CLD ; Clear decimal mode
LDX #$FF ; Init stack pointer
TXS ;
; Quick RAM test 1 - test that 2 locations in page zero are usable
; as a pointer
; Writes AA then 55 to each location.
LDA #$AA ; Use 10101010 test pattern 1st time
l00: STA $0 ; Write
CMP $0 ; Test
BNE l01 ; Mismatch
STA $1 ; Write
CMP $1 ; Test
BNE l01 ; Mismatch
; Carry is set here from CMP above being equal
ROL ; Changes to 01010101 for 2nd time, carry set
BCS l00 ; Then Changes to 10101011 and exits, carry now clr
BCC l02 ; Branch always: Do proper RAM test
l01: exit ERR_RAM_QUICK ; Result - RAM Test 1 failed
; Full RAM Test (0x0002-0x02FF,0x0400-0xBFFF skips VIA locs and ROM)
; Writes AA then 55 to each location.
If you have DRAM read-write issues, this will definitely die at "ERR_RAM_QUICK" (a JMP loop to itself, placed so that the addresses will cycle as described above).
As iss's ROM "does not need RAM", and works on your board, but mine specifically tests RAM first, and (hopefully) put up the error code on the addressbus, then we're still circling an inability to read and write RAM properly.