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Clock problems

Posted: Wed Jul 19, 2017 10:30 pm
by Vampire
So I'm trying to connect an Oric Atmos up to an FPGA, but I'm having some problems with the clock. I was seeing some odd false triggering, so I've tried running Ø2 through a 74HCT244, but this is where it starts to get odd. Let me share the scope traces.

In all traces yellow is the Oric's Ø2 line as it enters my interface board pin (Pin 17 of the 244) and blue is the output of the 244 on pin3 (before it goes to the level shifters and onward to the FPGA board). I'm also hoping these image links work as it would only let me add 3 attachments, so I zipped them and attached for posterity
(308.64 KiB) Downloaded 238 times

This image is from the the points listed above with the FPGA board powered off

Next is with the FPGA turned on with it's default program (which I believe lets all the outputs connected to my interface float) as you can see, it's still clean, but there is a very small amount of noise starting on the Oric's Ø2.

Now we have the FPGA fired up with my program. All it does (in theory) is set the data and IRQ bidirectional lines to read and powers up the level shifters. The only trace we have here is the 244's output (for reasons outlined in the last picture). You can see an erroneous trigger on the clock, which is the problem I've been having (even before I put the 244 in)

Lastly, we have a scope of the incoming Ø2 from the Oric, along with the output from the 244. Note that the erroneous trigger is gone again (by just placing the scope lead on the pin) but there is a shit tonne of noise on the incoming Ø2 line now (but only when it's not asserted high).

I'm struggling to work out why doing anything with the FPGA is causing noise on the Ø2 signal coming FROM the Oric. Does anyone have any ideas of things I could try to resolve this. I thought that maybe it was a power supply issue, as my expansion powers the 5 volt side of the level shifters from the Oric, but they are powered up even with the FPGA powered down (no noise) and I have smoothing caps on that line too for safety. Why would scoping the clock make the erroneous triggers go away? I have heard that the Oric's Ø2 can be a pain because it doesn't assert well. I have a software fix on the FPGA to bring my generated clock forward to match the Ø2 clock properly, but that is being broken by the Ø2 clock not being clean.


Re: Clock problems

Posted: Thu Jul 20, 2017 8:20 am
by Chema

Wait until an expert hardware answers this, but let me point out that I made some tests with an oscilloscope when I got my Microdisc clone (Silicebit's) and I notice something very similar: a strange peak on phi2 that appeared sometimes.

In my case I think it was when the board read the floppy disk, but it also appeared when the board was plugged into the Oric, but with no power. I had the amplibus attached.

Have a look at the last picture in this post: ... p200056462

I was getting the signal from a test point in the controller board and it seemed that the peak disappeared once the board was powered (it only appeared then when accessing the floppy drive), so it surely was being filtered by the circuitry.

But it puzzled me how such high peak could appear in the Oric's clock.

Oh, and by the way, I had to put the probes in x10 mode, as their impedance was filtering the phi2 signal captured by the oscilloscope. Can't remember who told me, but someone did :)

Re: Clock problems

Posted: Fri Jul 21, 2017 2:03 am
by Godzil
Phi2 have to be buffered, this is neither a TTL or a CMOS signal, but an unbuffered signal inside the 6502. By the way the original 6502 is using NMOS logic, which is neither CMOS not TTL and is in fact not completely compatible.

I mean it compatible is or the Oric would not work at all, but the output level or input level are not the same threshold as TTL/HCT, CMOS have.

Load on that signal is going to create lots of problem, like lots noise.
It is normally recommended to have the shortest possible path between Phi2 and the buffer (could be a simple transistor as done by Oric France), the longer the path the more noise and other effect may happen.

The spike you see is probably because the output is not buffered/filtered as it should be like other output from the 6502, it probably happen under load, on Phi2 or not necessarily.

A scope probe act like a capacitor, it can smooth signal if it is incorrectly set (like x1 vs x10) it also, like chema, have an impedance. Anyway as the 6502 have a really weak output, probing Phi2 with a scope can cause weird effect because that output is really not made at all to drive something without being properly buffered.

Try using a Schmitt Trigger buffer with compatible input voltage, that should solve part of the problem, especially if your buffer is not just next to the expansion port.

If you look at the 6502 datasheet you will see the Vo and Vi needed: ... y_1976.pdf

VIL (input low) is maximum VSS + 0.2 so 0.4V
VIH (input high) is minimum VCC-0.2 so 4.7V

Also, what is the analog bandwitdh and sample rate of your scope? the waveform is really choppy it should be way more smooth than that, are you using a PC based scope?

Re: Clock problems

Posted: Sat Jul 22, 2017 11:23 am
by Vampire
Hi Chema/Godzil,

Good call on the probe capacitance. I tried again with the probes set to x10 (and I don't know why I didn't think to try that earlier as I remembered having to do something similar in the past with the Oric) and got this...
Bad Trigger Small.jpg
From this you can clearly see that the noise on the clock is causing the erroneous trigger in the 74HCT244 (Highspeed Cmos Ttl compatible) at about 0.8v, which is a little odd as this shouldn't be triggering high till 2v according to the TTL spec. That said, it could be a spike that my scope is just too low resolution to capture. I figured that the 244 would be enough to clean the signal up, but I was wrong :oops:

The scope I'm using is a 50mhz SainSmart PC scope. This is mainly because most of my tooling here is on a budget. It does what I need, but extra resolution would have been good.

I had read previously that the Oric clock could be troublesome and also about using short signal cables (for the RGB=>SCART cable) but didn't put two and two together. You can see that there is going to be a problem as soon as you look at my setup ;)
I'll look into a Schmitt Trigger buffer, though those voltages are confusing based on what I'm seeing on the scope, and let you know how it turns out...