ORIC NEXT

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This includes generic Oric talkings and things that are totaly unrelated but want to share with people here :)
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Magoric
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Re: ORIC NEXT

Post by Magoric »

Today I have been thinking while working. I want the complete experience. So I'm going to opt for the hard way, but an affordable way for me.

Decisions:
- I'm going to design a 16 bits CPU. (Yes, the Oric next will be 16 bits.) but retro compatible with 6502 (At instructions).

Why? Because more wouldn't have the spirit of retro and less would be limited, and for that we have the real Oric. If I design it I can do without limitations of a comercial hardware and avoid limitations in the market, and avoid comercial rights. But I can copy/duplicate the aspects I think are importants.

As soon as I can I will put here the instructions set, the way to operate in 16 bits mode, the registers, etc. for you to analyze and tell me what you think.

- Structured Basic (without line number [I hate goto command. It makes spaghetti code and make it very hard to administer ] ) will be the computer language. This will have an ASM inline. Will be interpreted (this I have not clear at this moment), but sure will have compiler, maybe as application or maybe as option. Why? Because Basic is associed to retrocomputers (except Jupiter ace, but this is another history), is the language of original Orics and it's great to learn programming for child. Every body would kill for an ASM inline as commands of the interpreter of Basic in his moment. I, the first, and I want it.

I know this is the boring part. But be patience. It just starting. "Him" is brewing. :)
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Magoric
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Re: ORIC NEXT

Post by Magoric »

I have been working in the CPU concept. I want to develop it using a microcontroller like arduino and some others complementary chips. Nothing special, and easy to implement.

Here I show what I have for now in my desing paper, and I would like you tell me if you like what you read:

Magoric 6516. Theorical develop paper.

16 bits CPU compatible with MOS6502.
24 bits address.

Adicional Registers
- i (index) (8 bits). This register complement the z registers.
- Z (16bits) with index. There are 256 registers Z, indexed by ‘i’ register and in some times, by X, or Y registers. Z[0] will act as 16 bis accumulator.

The CPU will act as 8 and16 bits at the same time. Thats means that you can use instructions and registers of 8 and 16 bits in the same code.

How it works? The CPU read the next instruction from memmory indexed by the program counter. If the the first byte is $xx, that means instruction of 16 bits. Otherwise its an 8 bit instruction. Always will read 2 bytes. If the first byte is an 8 bit instruction, just use the other byte as usual.

The CPU will have a read buffer to load instructions and data as is needing.

The 16 bits zero page will be from $0000 to $FFFF

A new mode is added: Register.

New Instruction set:

[ADC Add with carry] Over Z[0] that acts as 16 bits accumulator.

Inmediate ADC #$1234
Zero Page ADC $1234
Zero Page, Z ADC $1234,Z [The Z indexed by i]
Absolute ADC $12345678
Absolute, Z ADC $12345678,Z [The Z indexed by i]
Indexed Indirect, Z ADC ($1234, Z) [The Z indexed by i]
Indirect Indexed, Z ADC ($1234),Z [The Z indexed by i]

[AND bitwise AND with accumulator] Over Z[0] that acts as 16 bits accumulator.

Inmediate AND #$1234
Zero Page AND $1234
Zero Page, Z AND $1234,Z [The Z indexed by i]
Absolute AND $12345678
Absolute, Z AND $12345678,Z [The Z indexed by i]
Indexed Indirect, Z AND ($1234,Z) [The Z indexed by i]
Indirect Indexed, Z AND ($1234),Z [The Z indexed by i]

[ASL (Arithmetic Shift Left) ] Over Z[0] that acts as 16 bits accumulator.

Acumulator ASL Z [Z[0]]
Zero Page ASL $1234
Zero Page, Z ASL $1234,Z [The Z indexed by i]
Absolute ASL $12345678
Absolute, Z ASL $12345678,Z [The Z indexed by i]

BIT (test BITs)

Zero Page ASL $1234
Absolute ASL $12345678

Branch Instructions. All have 16 bits jumps.
BPL (Branch on PLus)
BMI (Branch on MInus)
BVC (Branch on oVerflow Clear)
BVS (Branch on oVerflow Set)
BCC (Branch on Carry Clear)
BCS (Branch on Carry Set)
BNE (Branch on Not Equal)
BEQ (Branch on EQual)
CMP (CoMPare accumulator)

Inmediate CMP #$1234
Zero Page CMP $1234
Zero Page, Z CMP $1234,Z [The Z indexed by i]
Absolute CMP $12345678
Absolute, Z CMP $12345678,Z [The Z indexed by i]
Indexed Indirect, Z CMP ($1234,Z) [The Z indexed by i]
Indirect Indexed, Z CMP ($1234),Z [The Z indexed by i]
Register CMP Z [The Z indexed by i]
CPZ (ComPare Z register) [The Z indexed by i]

Inmediate CMP #$1234
Zero Page CMP $1234
Absolute CMP $12345678

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Dbug
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Re: ORIC NEXT

Post by Dbug »

Zero Page ADC $1234
The whole point of zero page access is just to make the code faster by not having to specify the high byte, so I guess what you meant is the standard "ADC $12" but it would use the values at addresses $12 and $13 as a 16bit value, correct?
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Re: ORIC NEXT

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Personally, before extending the instruction set to 16bit, I would fix the glaring problems (which have been fixed on other variants of the 6502), like
- No "Store Zero" instruction, which means you need to waste registers just to clear a byte
- No "Branch Always" (BRA), so making 100% relocated code forces you to do double relative branches because JMP is absolute
- No Branch to Subroutine" (BSR), same issue as BRA
- Only able to shift by one, being able to shift by "n" values, would be very nice
- Impossible to ROL on just 8 bit, the carry is always involved which makes it unpractical in some situations
- Not possible to move the stack or the zero page, makes interrupt handlers or multi-tasking difficult
- No INC or DEC for the accumulator, which mens you need to clc/add #1 or sec/sbc #1 all the time
- No PHX/PHY/PLX/PLY, so you have to TXA/PHA/TYA/PHA and PLA/TAY/PLA/TAX to save and restore index registers

One of these improved CPU is the one found in the Nec PC Engine:
http://shu.emuunlim.com/download/pcedocs/pce_cpu.html
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Re: ORIC NEXT

Post by jbperin »

I don't understand the $ to distinguish between 8 and 16 bits. Usually, $ is used to introduce hexa decimal value. How do you switch between decimal and hexadecimal?

The address is supposed to be 24 bits but values $12345678 are 32 bits wide.

I militate for the introduction of a Test And Set instruction

https://en.m.wikipedia.org/wiki/Test-and-set

It's a must have for multi tasks with shared resources.
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Magoric
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Re: ORIC NEXT

Post by Magoric »

Dbug wrote: Fri Feb 12, 2021 8:06 am
Zero Page ADC $1234
The whole point of zero page access is just to make the code faster by not having to specify the high byte, so I guess what you meant is the standard "ADC $12" but it would use the values at addresses $12 and $13 as a 16bit value, correct?
Correct
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Magoric
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Re: ORIC NEXT

Post by Magoric »

Dbug wrote: Fri Feb 12, 2021 8:18 am Personally, before extending the instruction set to 16bit, I would fix the glaring problems (which have been fixed on other variants of the 6502), like
- No "Store Zero" instruction, which means you need to waste registers just to clear a byte
- No "Branch Always" (BRA), so making 100% relocated code forces you to do double relative branches because JMP is absolute
- No Branch to Subroutine" (BSR), same issue as BRA
- Only able to shift by one, being able to shift by "n" values, would be very nice
- Impossible to ROL on just 8 bit, the carry is always involved which makes it unpractical in some situations
- Not possible to move the stack or the zero page, makes interrupt handlers or multi-tasking difficult
- No INC or DEC for the accumulator, which mens you need to clc/add #1 or sec/sbc #1 all the time
- No PHX/PHY/PLX/PLY, so you have to TXA/PHA/TYA/PHA and PLA/TAY/PLA/TAX to save and restore index registers

One of these improved CPU is the one found in the Nec PC Engine:
http://shu.emuunlim.com/download/pcedocs/pce_cpu.html

Your aport is very valuable. Thanks!. I will add the instructions to solve thats problems.

The link was very interesting. I'm goin to study this propose to extract the most interesant and add it to this desing.
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Magoric
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Re: ORIC NEXT

Post by Magoric »

Thank you for your aport.
jbperin wrote: Fri Feb 12, 2021 8:23 am I don't understand the $ to distinguish between 8 and 16 bits. Usually, $ is used to introduce hexa decimal value. How do you switch between decimal and hexadecimal?
All the time you were reading hexadecimal numbers. $12345678 is just a number like $AB12FF95. If you type an 8 bit number the assambler will interpret this as 8 bit number. If you do it with 16, will be 16. The final instruction code will be difefent for 8 than for 16, and obviusly, the range of the data. If you want to put an instruction of 16 with, for example, a value of 1, then you put in the code "instruction $0001" for 16 bits. The same for 8 bits "instruction $01". And the equivalent for the address.
The address is supposed to be 24 bits but values $12345678 are 32 bits wide.
Well, I dont know how to fix this. Formaly, the concept is 32 bits, but I limitate the bus to 24 bits, because with this range is a lot of more than suficient for this project. But I don't want to limitate the theorical range of the instructions to the limited bus.
I militate for the introduction of a Test And Set instruction

https://en.m.wikipedia.org/wiki/Test-and-set

It's a must have for multi tasks with shared resources.
Good point in both sens. I had didn't think in multitask. I will meditate about it.
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Magoric
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Re: ORIC NEXT

Post by Magoric »

I've thinked about to add shadow registers: A system to copy all the registers with an only one instruction. And restore them with another one.

What do you think?
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Re: ORIC NEXT

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Magoric wrote: Fri Feb 12, 2021 12:16 pm I've thinked about to add shadow registers: A system to copy all the registers with an only one instruction. And restore them with another one.

What do you think?
I'm no expert on these things, so I may be saying impractical things :)
If the idea is to experiment with new ideas, what about having an internal 8 bit register which would be a "context id", just changing the value would swap to an entire set of values, including all the registers, the status register, stack pointer and base address, zero page base address, and with some instructions to copy the values of any context to the current context, of the current context copied to any other.

Basically that could be used to handle up to 256 hardware threads with all their own context, but also could be used to run subroutines with pre-set zero page content, dedicated stack pointer and address, so you can use that to do fast graphic routines (like for example map the stack to the zero page to quickly generate content using push and pop, or to the screen, etc...).

I guess the IRQ should by default to a specific context page, like say "page 255" is the IRQ page, while BRK should keep using the current context page so you can modify the calling parameters, access what's indexed, etc... which bring the topic of IRQ: If you want your super CPU to be awesome, should provide a way to have a different handler for the various interrupt sources, because that's a major pain on the 6502 :)
Good point in both sens. I had didn't think in multitask. I will meditate about it.
Having a faster cpu with more memory, you have to be able to run multiple stuff at the same time, so yes makes sense to have some ways to do atomic updates without having to SEI/CLI all the time.
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Magoric
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Re: ORIC NEXT

Post by Magoric »

Yes. It is to expand the idea. But, I have to think about it, beacuse What is the limit? I want to do a new machine, but not a current machine. For that, we have a lot CPUs to choose.
In any way, it is a good point.

I will think about it.

Thank you!!
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Magoric
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Re: ORIC NEXT

Post by Magoric »

Dbug wrote: Fri Feb 12, 2021 8:18 am Personally, before extending the instruction set to 16bit, I would fix the glaring problems (which have been fixed on other variants of the 6502), like
- No "Store Zero" instruction, which means you need to waste registers just to clear a byte
- No "Branch Always" (BRA), so making 100% relocated code forces you to do double relative branches because JMP is absolute
- No Branch to Subroutine" (BSR), same issue as BRA
- Only able to shift by one, being able to shift by "n" values, would be very nice
- Impossible to ROL on just 8 bit, the carry is always involved which makes it unpractical in some situations
- Not possible to move the stack or the zero page, makes interrupt handlers or multi-tasking difficult
- No INC or DEC for the accumulator, which mens you need to clc/add #1 or sec/sbc #1 all the time
- No PHX/PHY/PLX/PLY, so you have to TXA/PHA/TYA/PHA and PLA/TAY/PLA/TAX to save and restore index registers
Ok, I have been a little busy, but I continue the voyage looking for the Oric Next. This is the new 8 bit instructions I am going to implement based on your suggestions:

New 8 bits Instruction set:

[BRA BRanch Always]
Inmediate BRA $01

[BRS BRanch Subrutine]
Inmediate BRS $01

[A REGISTER INC/DEC]
Implied INA
Implied DEA

[STACK INSTRUCTIONS]
Implied PHX
Implied PLX
Implied PHY
Implied PLY

[ RNR (RouNd Right) ]
Affects Flags: N Z C
MODE SYNTAX
Accumulator RND A
Zero Page RND $12
Zero Page,X RND $12,X
Absolute RND $1234
Absolute,X RND $1234,X

[ RNL (RouNd Left) ]
Affects Flags: N Z C
MODE SYNTAX
Accumulator RNL A
Zero Page RNL $12
Zero Page,X RNL $12,X
Absolute RNL $1234
Absolute,X RNL $1234,X

- I think that to add an instruction set to put zero in a memory byte is to complex the system for a little benefit. I consider more efficient to put a specific value, but I am still thinking about it.
- I can't see the Multiple shiftting, but I don't renounce on this by the momment..
- If I move the zero page, I will make a retro incompatible CPU. I want to make a 100% 6502 compatible CPU. For multitask I'm going to use your idea (or part of it) to make multiple environments to save the complete state.

Thank you for all your suggestions.
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Re: ORIC NEXT

Post by Dbug »

Magoric wrote: Wed Feb 24, 2021 10:24 pm [BRS BRanch Subrutine]
Inmediate BRS $01
Generally that one is called BSR (Branch Sub Routine), and that matches JSR :)
- If I move the zero page, I will make a retro incompatible CPU. I want to make a 100% 6502 compatible CPU.
The idea is not to move the zero page, the idea is to add a register somewhere you can use to say where the zero page is (register that should be part of the context saving), so by default the zero page is still at address $0000 but technically can be moved (temporarily) anywhere.

People have been complaining a lot about the x86 segment registers, etc... but really there was quite a lot of good ideas in the cpu, the worse really was the syntax used, it was super verbose and hard to read, but conceptually it made it "relatively easy" to use a large amount of memory with quite little difficulty, as long as you could work with one more more 64kb pages.
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Magoric
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Re: ORIC NEXT

Post by Magoric »

Dbug wrote: Thu Feb 25, 2021 8:32 am Generally that one is called BSR (Branch Sub Routine), and that matches JSR :)
Good point. I name it to distinguish from the Jump version, but you are right
The idea is not to move the zero page, the idea is to add a register somewhere you can use to say where the zero page is (register that should be part of the context saving)
I will think about it.
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Magoric
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Re: ORIC NEXT

Post by Magoric »

Hello.

I have started to develop the micro.

What I am going to do is to use a microcontroller to emulate the micro. This have the advantage that I can reuse the code I will make for the emulator (using C).

The idea is to make first an emulated machine before the phisical computer, but will be parallel work, because when I finish the emulated version of the micro (and the tests with the easily of a PC compiler) I will try to port it to the microcontroller.

This will let me see easily if what i develop is working or not.

Anyway, I will put here every step of the develop, because, your help and your comments are very, very important for the goal, that is to enhance the ORIC.
Last edited by Magoric on Mon Mar 01, 2021 1:36 am, edited 1 time in total.
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