Hardware upgrade for the Oric?

This is the right place to discuss on how to implement hardware vsync, adding a VIA or AY chipset, puting multiple roms, or how to design a new flash expansion card.
JamesD
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Post by JamesD » Tue Oct 02, 2007 1:51 am

Ok, the ULA seems to have three very useful outputs (thank you whoever implemented the ULA in VHDL):
CSROMn
CSRAMn
CSIOn

Here is the slightly modified VHDL controlling those lines:

------------------------------
-- PAGE I/O : 0x300-0x3FF
CSIOn <= '0' WHEN (ADDR(7 downto 0) = "00000011") AND (CLK_1 = '1') ELSE '1';

-- PAGE ROM : 0xC000-0xFFFF
CSROMn <= '0' WHEN (ADDR(7 downto 6) = "11" AND MAPn = '1' AND CLK_1 = '1') ELSE '1';

-- PAGE RAM : the rest ...
CSRAMn <= '0' WHEN (ADDR(7 downto 6) = "11" AND MAPn = '0'AND CLK_1 = '1')
OR
( (ADDR(7 downto 0) /= "00000011" OR ADDR(7 downto 6) /= "11")
AND MAPn = '1' AND CLK_1 = '1'))
ELSE '1';


--------------------------------
So CSROMn gets us on the hardware page during a clock.
We just have to check where on that page our hardware will respond. Once that's done we just latch the I/O line and output it to /ROMDIS... making sure it starts up with /ROMDIS inactive so the ROM actually gets booted.

This should all fit in a single PAL/GAL thanks to the CSROMn.

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Post by mmu_man » Tue Oct 02, 2007 12:40 pm

Theoric had an issue named "Accès à la RAM overlay" with a board design that did it.

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Post by JamesD » Tue Oct 02, 2007 5:26 pm

mmu_man wrote:Theoric had an issue named "Accès à la RAM overlay" with a board design that did it.
Issue #5 available here, pages 40-43:

http://www.oric.org/index.php?page=ress ... tail&id=69

It's a pretty big board since it is all standard chips and has to decode all the address lines.

I don't know French but it looks like the comments on page 42 say the page is flipped by writing 0 or 1 to $03FF. 0 = RAM, 1 = ROM

I *think* I could do this with one PAL/GAL.
I thought about using I/O to switch based on READ or WRITE but D0 would work fine and would be compatible with the existing board.

Inputs would be:
CSIOn (clock and upper address byte test from ULA, #$03xx)
A0-A7 (all must be active, #$xxFF)
D0 (to be latched and output to /ROMDIS)
Power
GND
Outputs would be:
/ROMDIS

This would be a VERY cheap and easy mod.
A board could plug in place of a ROM, the ROM then plugs into it and it has 1 wire with a small clip to attach to the ULA.
A0-A7 comes from the ROM socket
/ROMDIS goes to the ROM socket pin 27
The wire attaches to CSIOn with the clip.
A jumper on the board could sit between the /ROMDIS output of the chip and pin 27 so it could be disabled.

BTW, replacing the internal ROMs with FLASH that port could be used to page through the FLASH.

I'll have to think about the serial connections for MMC and RS232 to the PC. That may not fit under a ROM and would require replacing it with FLASH. The board *should* still fit in the ROM area though.
Or the MMC could be skipped and stuff could be just stored in unused pages of the FLASH chip.

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Post by JamesD » Tue Oct 02, 2007 5:35 pm

After looking at the schematic I don't see anything resembling a CSIOn line.
In fact, to keep the ULA simple it looks like external logic was used on the address line outputs from the ULA so I doubt any of those 3 signals exist on the ULA.

However, with an additional board that plugs in the ULA socket and the ULA plugs into it we could generate the CSIOn signal.

Inputs
CLK
A8-A15
Power
GND
Output
CSIOn (using exactly the same logic as the VHDL ULA)

An 8 input AND plus an inverter should be all that's needed logic wise.
Or another PAL.
Last edited by JamesD on Tue Oct 02, 2007 5:44 pm, edited 1 time in total.

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Post by JamesD » Tue Oct 02, 2007 5:40 pm

One more thing... using D0 to select ROM or RAM would reduce the size of the page register by 1 bit, effectively cutting the maximum page area to 2MB.

(127 x 16KB = 2MB)

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Post by JamesD » Tue Oct 02, 2007 6:08 pm

After looking at the diagram from the circuit in Theoric it appears as if /ROMDIS is not used at all but /MAP is.
I can also see that /ROMDIS only goes to the ROMs on the schematic.

That means that:
/MAP switches to overlay RAM and disables the internal ROM.
/ROMDIS only disables the internal ROMs.

If /MAP is inactive and /ROMDIS is inactive the internal ROMs are active
If /MAP is active, the RAM overlay is active and the internal ROM is inactive
If /MAP is inactive and /ROMDIS is active that memory area goes away unless some external memory is addressed there.

That means the circuit at the ULA has to have an input from the circuit at the ROM and output to /MAP.
The circuit at the ROM ignores /ROMDIS and outputs to a line going to the circuit at the ULA.

The circuit at the ULA adds the external input and outputs to pin 26 of the ULA. It would still provide the other output for use with the serial port and MMC interface.

I'll have to think about this a while to be sure this is correct.

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Post by mmu_man » Wed Oct 03, 2007 12:30 am

Right I knew /MAP and /ROMDIS were handled oddly but I didn't recall it that weird.
IIRC /ROMDIS goes straight to one of the ROM's CE.
To have something more expandable one should do like the Telestrat does, have an n-bit (3 for telestrat) register that latches the bank page number.
Then IIRC page 0 is overlay ram, the rest are mapped to cartridges.
It's easy to check for 0, just OR all 8 bits, the result is 0 if all bits are 0.
For 8 bits that leaves 255 pages, =4MB-16KB.
It'd be nice if it was compatible with telestrat, but I think other bits are used (it's on a port on the 2nd VIA)... indeed no bit left.

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Post by JamesD » Wed Oct 03, 2007 1:04 am

mmu_man wrote:Right I knew /MAP and /ROMDIS were handled oddly but I didn't recall it that weird.
Actually it's not so much weird as simple. The design has simple written all over it. Simple = cheap.
IIRC /ROMDIS goes straight to one of the ROM's CE.
To have something more expandable one should do like the Telestrat does, have an n-bit (3 for telestrat) register that latches the bank page number.
Then IIRC page 0 is overlay ram, the rest are mapped to cartridges.
It's easy to check for 0, just OR all 8 bits, the result is 0 if all bits are 0.
For 8 bits that leaves 255 pages, =4MB-16KB.
It'd be nice if it was compatible with telestrat, but I think other bits are used (it's on a port on the 2nd VIA)... indeed no bit left.
Hmmm... I was thinking of that but decided against it for some reason and now I haven't the slightest idea why. It doesn't even make sense not to do it that way.

Does the telestrat switch at the same address? (I'd hope so)

Well,
step one... get the bank select working.
step 2 FPGA? FLASH? Serial port? SD/MMC interface? Just baby steps... noting too big. (rolling eyes)
step 3 who wants to write the DOS?

Oh wait, I still need to build a power supply for this Oric and I don't even know if it works since it's never been on. I hope I still have a monitor that will hook to this.

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Post by mmu_man » Wed Oct 03, 2007 1:47 am

JamesD wrote:Does the telestrat switch at the same address? (I'd hope so)
step one... get the bank select working.
it's ORA [2-0] of VIA2, but as I said it uses other bits, so we should leave it alone.
Ideally there would be a way to mutually exclude each extention so it would work on telestrat. It should be so that the reset value (like 0xff) disables it to let the ROM boot (could be useful), and let other hw (including drives) select overlay. I'm not sure if /MAP and /ROMDIS are to be used as open-collector or via a mux though.
JamesD wrote:step 2 FPGA? FLASH? Serial port? SD/MMC interface? Just baby steps... noting too big. (rolling eyes)
FPGA doesn't provide storage on its own (except some ram cells), could help on the logic but is expensive. Another option is to use an uC.
Flash devices accessed on parallel bus is easier to use (compact flash cards can emulate IDE device).
serial cards OTH require something to handle the protocol (the 6502 might be too slow).
JamesD wrote:step 3 who wants to write the DOS?
I still want to patch sedoric to run on my Jasmin, so maybe later :P

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Post by JamesD » Wed Oct 03, 2007 5:20 am

mmu_man wrote:
JamesD wrote:Does the telestrat switch at the same address? (I'd hope so)
step one... get the bank select working.
it's ORA [2-0] of VIA2, but as I said it uses other bits, so we should leave it alone.
Ideally there would be a way to mutually exclude each extention so it would work on telestrat. It should be so that the reset value (like 0xff) disables it to let the ROM boot (could be useful), and let other hw (including drives) select overlay. I'm not sure if /MAP and /ROMDIS are to be used as open-collector or via a mux though.
Given the rarity of the Telestrat and the differences... I'm not sure it's practical to support it. If it's ULA changed at all then I'd say it's a given Telestrat owners are on their own. How many other Oric fans would want the thing in the first place? Would it even top 50?
JamesD wrote:step 2 FPGA? FLASH? Serial port? SD/MMC interface? Just baby steps... noting too big. (rolling eyes)
FPGA doesn't provide storage on its own (except some ram cells), could help on the logic but is expensive. Another option is to use an uC.
Flash devices accessed on parallel bus is easier to use (compact flash cards can emulate IDE device).
serial cards OTH require something to handle the protocol (the 6502 might be too slow).
JamesD wrote:step 3 who wants to write the DOS?
I still want to patch sedoric to run on my Jasmin, so maybe later :P
Actually, I meant a PLD which would probably cost under $5US. $10 max. If I were going with a full blown FPGA I'd just work on an ORIC in a chip.
A FLASH chip will cost around $15 for a decent sized one. With everything it would probably have to cost $50 if boards were produced.
However, if someone wanted to do it themselves it would just cost the price of the chips. Under $30.
That's what? 20 Euros? Maybe 15 by tomorrow with the way the dollar is going.

Sure, IDE has an 8 bit interface but it's HUGE by comparison, it would be more difficult to squeeze inside, has many more wires and CF/MMC also has an 8 bit interface if you drive it with a UART. Either would be faster than the ORIC needs.

A uC takes this out of the realm of being an internal upgrade and the cost increases as well.

BTW, IDE and CF/MMC interfaces operate at whatever speed they are clocked. They are asynchronous. Both have been made to work on 6502 machines before.

And with as many projects as I have lined up... trying to write a DOS that still runs old software for a machine that I quite frankly had no knowledge of at all until recent years? I'm not the best person for that job.
I could write routines to read, write and erase. After that someone else that's poked around in the existing dos would be better.

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Post by Dbug » Wed Oct 03, 2007 6:05 pm

For the DOS, all there is need for is basicaly to work from what Fabrice Frances did: Use an existing Oric DOS (Randos, Sedoric, ...) and just adapt the low level access code.

For Sedoric, there are a lot of people in the Club Europe Oric who have pretty good knowledge of Sedoric internals, and could easily show where the read, write, seek, format etc... code is done.

Of course the easiest way from a software point of view would be to emulate the microdisc + fdc electronics, because then demos and games that do direct access to the disc drive would work.

Else well, patch an existing os is the simplest way :)

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Post by mmu_man » Wed Oct 03, 2007 9:44 pm

Dbug wrote:For the DOS, all there is need for is basicaly to work from what Fabrice Frances did: Use an existing Oric DOS (Randos, Sedoric, ...) and just adapt the low level access code.

For Sedoric, there are a lot of people in the Club Europe Oric who have pretty good knowledge of Sedoric internals, and could easily show where the read, write, seek, format etc... code is done.
Except existing DOSes have limitations on the media size (sector count, ...), I'm not sure it would handle 1MB. I read some Apple II stuff the other day, and it seems sometimes they formated harddrives as a lot of floppy-sized partitions to make them usable. In either case, it's still needs a support program to be used on PC. (should be possible to make a sedoricfs module for linux and other though)
Another option is to write a FAT-compatible DOS, but it's a bigger undertaking.
Of course the easiest way from a software point of view would be to emulate the microdisc + fdc electronics, because then demos and games that do direct access to the disc drive would work.
Could reuse a floppy emulator like http://www.silicium.org/forum/viewtopic.php?t=17033 but it's quite complex.

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Post by mmu_man » Wed Oct 03, 2007 9:50 pm

Dbug wrote:For Sedoric, there are a lot of people in the Club Europe Oric who have pretty good knowledge of Sedoric internals, and could easily show where the read, write, seek, format etc... code is done.
The microdisk specific stuff is quite isolated, except for the overlay switching, cf. http://revolf.free.fr/oric/sedoric.zip

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Post by JamesD » Thu Oct 04, 2007 5:22 am

There is existing FAT code for the Apple that could be used as a start.
The sedoric code may very well be an excellent disassembly but it's a bit sparse on comments.

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Post by JamesD » Fri Oct 05, 2007 5:57 am

Just an FYI... I can buy 1GB SD FLASH cards for $10, 1GB MicroSD cards for $14 or 1GB Compact FLASH cards for $15. $15 is currently something like 10 Euros.
Hmmmm... MicorSD would definately fit inside an ORIC. It has the same interface as SD but smaller. A cheap socket might even fit on the bottom side of a board that plugs in between the ROM and the ROM socket.

Some useful stuff
http://hubbard.engr.scu.edu/avr/avrlib/ ... __mmc.html
http://www.hdf-group.org/UG41r3_html/SDS_SD.fm2.html
http://sourceforge.net/projects/efsl/

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