Clock problems
Posted: Wed Jul 19, 2017 10:30 pm
So I'm trying to connect an Oric Atmos up to an FPGA, but I'm having some problems with the clock. I was seeing some odd false triggering, so I've tried running Ø2 through a 74HCT244, but this is where it starts to get odd. Let me share the scope traces.
In all traces yellow is the Oric's Ø2 line as it enters my interface board pin (Pin 17 of the 244) and blue is the output of the 244 on pin3 (before it goes to the level shifters and onward to the FPGA board). I'm also hoping these image links work as it would only let me add 3 attachments, so I zipped them and attached for posterity .
This image is from the the points listed above with the FPGA board powered off
Next is with the FPGA turned on with it's default program (which I believe lets all the outputs connected to my interface float) as you can see, it's still clean, but there is a very small amount of noise starting on the Oric's Ø2.
Now we have the FPGA fired up with my program. All it does (in theory) is set the data and IRQ bidirectional lines to read and powers up the level shifters. The only trace we have here is the 244's output (for reasons outlined in the last picture). You can see an erroneous trigger on the clock, which is the problem I've been having (even before I put the 244 in)
Lastly, we have a scope of the incoming Ø2 from the Oric, along with the output from the 244. Note that the erroneous trigger is gone again (by just placing the scope lead on the pin) but there is a shit tonne of noise on the incoming Ø2 line now (but only when it's not asserted high).
I'm struggling to work out why doing anything with the FPGA is causing noise on the Ø2 signal coming FROM the Oric. Does anyone have any ideas of things I could try to resolve this. I thought that maybe it was a power supply issue, as my expansion powers the 5 volt side of the level shifters from the Oric, but they are powered up even with the FPGA powered down (no noise) and I have smoothing caps on that line too for safety. Why would scoping the clock make the erroneous triggers go away? I have heard that the Oric's Ø2 can be a pain because it doesn't assert well. I have a software fix on the FPGA to bring my generated clock forward to match the Ø2 clock properly, but that is being broken by the Ø2 clock not being clean.
P.
In all traces yellow is the Oric's Ø2 line as it enters my interface board pin (Pin 17 of the 244) and blue is the output of the 244 on pin3 (before it goes to the level shifters and onward to the FPGA board). I'm also hoping these image links work as it would only let me add 3 attachments, so I zipped them and attached for posterity .
This image is from the the points listed above with the FPGA board powered off
Next is with the FPGA turned on with it's default program (which I believe lets all the outputs connected to my interface float) as you can see, it's still clean, but there is a very small amount of noise starting on the Oric's Ø2.
Now we have the FPGA fired up with my program. All it does (in theory) is set the data and IRQ bidirectional lines to read and powers up the level shifters. The only trace we have here is the 244's output (for reasons outlined in the last picture). You can see an erroneous trigger on the clock, which is the problem I've been having (even before I put the 244 in)
Lastly, we have a scope of the incoming Ø2 from the Oric, along with the output from the 244. Note that the erroneous trigger is gone again (by just placing the scope lead on the pin) but there is a shit tonne of noise on the incoming Ø2 line now (but only when it's not asserted high).
I'm struggling to work out why doing anything with the FPGA is causing noise on the Ø2 signal coming FROM the Oric. Does anyone have any ideas of things I could try to resolve this. I thought that maybe it was a power supply issue, as my expansion powers the 5 volt side of the level shifters from the Oric, but they are powered up even with the FPGA powered down (no noise) and I have smoothing caps on that line too for safety. Why would scoping the clock make the erroneous triggers go away? I have heard that the Oric's Ø2 can be a pain because it doesn't assert well. I have a software fix on the FPGA to bring my generated clock forward to match the Ø2 clock properly, but that is being broken by the Ø2 clock not being clean.
P.